AMIQ: Jitter at the memory end			FAQ overview
Question:		There is a jitter at the end of the signal (every 2 minutes).
Answer:		Jitter appears because of the wrap-around problem. This occurs when the sequence, which is called from the memory, starts at a voltage level different from the one where it stops. The repetition of the jitter depends on the clock rate of the signal.Chapter 4 of the WINIQSIM Application Manual describes solutions for different modulation types.