Signal integrity test

Signal integrity test

Verify the signal integrity in your digital design

Signal Integrity is essential for the correct functioning of all interfaces in your digital design. It is highly influenced by the reference clock provided through the clock tree, the transmitter and receiver implementation in the chip, as well as the frequency response, reflections and cross-talk of the signal traces.

With expertise in both the time and frequency domains, and by working closely with the corresponding standardization bodies, Rohde&Schwarz provides a wide range of solutions for

  • Interface test
  • Clock Tree, PLL and ADC/DAC test
  • PCB and interconnect test

Interface test: documents and videos

DDR3 data eye diagram testing

When debugging DDR3 signals, tools like eye diagram, mask test and read/write separation are invaluable for efficient analysis. The R&S®RTx-K91 option includes a full tool set for all signal integrity issues from DDR3 system validation and debug, to compliance test.

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Triggering read and write cycles of DDR3 memories

Reliably separating read/write cycles is crucial for signal integrity analysis of DDR memory interfaces. The R&S®RTP digital trigger and zone trigger provide versatile and flexible triggering capabilities for tests on DDR memory interfaces.

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Realtime deembedding with the R&S®RTP

Deembedding the test fixtures and cables of a test setup is essential for valid measurements on digital interfaces. The R&S®RTP oscilloscope option K122 provides real-time deembedding to trigger and measure on the actual signal properties in real-time.

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Optimize differential measurements on high-speed interfaces

The R&S®RT-ZM modular probe system supports measurements in differential mode and common mode as well as single-ended measurements. The ground connection prevents the circuit from floating and ensures stable and reproducible signals.

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Faster debugging using specialized triggers

The digital trigger system in R&S oscilloscopes directly accesses the acquired samples in real-time, supporting a large selection of trigger conditions with an unrivaled accuracy.

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DDR3 signal integrity debugging
DDR3 signal integrity debugging with R&S®RTP

Signal Integrity debugging of a DDR3 signal, using R&S®RTP-K91 DDR3/LPDDR3 Signal Integrity Debug and Compliance test software.

Signal integrity debugging
Signal Integrity debugging with R&S®RTP on a USB 3.1 device

Eye diagram measurements on a USB 3.1 Gen1 interface, with an R&S®RTP oscilloscope. Includes mask tests and eye measurements such as eye height, eye width and jitter histogram.

USB 3.1 interface debug with realtime deembedding
USB 3.1 Gen1 interface debug with realtime deembedding

Signal Integrity measurements on a USB 3.1 Gen1 Interface. The R&S®RTP oscilloscope option K122 provides real-time deembedding to trigger and measure on the actual signal properties, in real-time.

Realtime deembedding
Realtime deembedding with the R&S®RTP

Realtime Deembedding of a signal path with R&S®RTP oscilloscope option K122. Trigger on signal events only detectable in a deembedded signal.

Signal integrity measurements with jitter analysis
Jitter analysis with R&S®RTO

Measurement of TIE jitter with R&S®RTO oscilloscope option K12. Analysis of TIE jitter of a clock signal in statistics, track, histogram and spectrum view, to detect disturbances on the clock.

Industry-leading mask test: quick configuration – reliable results
Industry-leading mask test: quick configuration - reliable results

Measurements with eye diagrams, and definition of eye masks with R&S®RTO. Mask tests quickly reveal whether a specific signal lies within defined tolerance limits, providing pass/fail evaluation of the device under test.

Clock tree, PLL and ADC/DAC test: documents and videos

Verifying additive phase noise and jitter attenuation of PLLs

SerDes PLLs in high-speed digital SoCs need to be designed for ultra-low jitter. Due to its high phase noise sensitivity, the R&S®FSWP phase noise analyzer is the instrument of choice for these tests.

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Verifying the true jitter performance of PCIe Refclks

With growing data rates, the jitter limits for PCIe Refclks are getting tighter. Due to their superior jitter sensitivity, the PCIe Gen5 specification has introduced Phase Noise Analyzer based testing to verify the true jitter performance of a Refclk.

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Measuring power supply noise rejection (PSNR)

Low jitter oscillators and clocks deliver best performance with clean power rails. As part of an overall system design, they also have to perform in a non-ideal power integrity environment and properly suppress power supply induced phase noise and jitter.

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Comparison of jitter measurements in time and frequency domain

Jitter can be measured in both time and frequency domain. While scope-based TIE measurements include all jitter types, phase noise analyzer based jitter measurements are restricted to clock signals; with an unrivalled jitter sensitivity.

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Verifying the clock source

The signal purity of clock sources has a direct impact on the overall system performance. To ensure proper operation, it is necessary to verify that the purity meets the design requirements.

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A 1 MHz to 50 GHz Direct Down-Conversion Phase Noise Analyzer with Cross-Correlation

The R&S®FSWP offers a frequency range from 1 MHz to 50 GHz with direct down-conversion, analog I/Q mixers and baseband signal sampling. The traditional PLL concept is replaced by a digital FM/AM demodulator for concurrent measurement of phase and amplitude noise.

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Measurement Setup for Phase Noise Test at Frequencies above 50 GHz

With external mixers, the R&S®FSWP offers phase noise measurements beyond 50GHz. Cross-correlation can be used to further reduce the internal phase noise contribution of the test setup.

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Advanced Techniques for Spurious Measurements with R&S FSW-K50

Spurious measurements require a carefull selection of the optimum resolution bandwidth (RBW). R&S®FSW-K50 automates the process of noise floor estimation, spur detection and spot search and selects the optimum RBW for each step.

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Jitter Analysis with the R&S®RTO Oscilloscope

Jitter is a main concern in Signal Integrity analysis. With the options R&S®RTP-K12 and R&S®RTO-K12, R&S oscilloscopes can measure TIE jitter, period jitter, cycle-cycle jitter, etc. and offer result displays like jitter track, histogram or spectrum.

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Signal integrity measurements with jitter analysis
Jitter analysis with R&S®RTO

Measurement of TIE jitter with R&S®RTO-K12. Analysis of TIE jitter of a clock signal in statistics, track, historgam and spectrum view to detect disturbances on the clock.

PCB and interconnect test: documents and videos

Precise measurements on high-speed digital PCBs with the R&S®ZNB

With the advanced time domain option, R&S®ZNB-K20, the R&S®ZNB provides accurate tests of eye diagram, rise time, skew, etc. on digital high-speed signal structures. Additional deembedding tools can be installed to remove the effects of lead-ins and lead-outs.

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Signal Integrity Measurements
Signal integrity measurements

In combination with the advanced time domain option R&S®ZNA-K20, the R&S®ZNA vector network analyzer offers a variety of Signal Integrity measurements, like eye diagram, rise time, skew, etc.. A USB-C cable is analyzed in frequency and time domain.

Eye diagram analysis with the R&S®ZNB: introduction
Eye diagram analysis with R&S®ZNB: Introduction

Measurement of eye diagrams and eye mask testing with the advanced time-domain option R&S®ZNB-K20. The option allows the analysis of jitter and noise as well as emphasis and equalization on the measured eye diagram.

Eye diagram analysis with the R&S®ZNB: how to set up the measurements
Eye diagram analysis with R&S®ZNB: How to set up the measurements

Measurement of eye diagrams and eye mask testing with the advanced time-domain option R&S®ZNB-K20. The option allows the analysis of jitter and noise as well as emphasis and equalization on the measured eye diagram.

Signal integrity testing on differential signal structures with the R&S®ZNB
Signal integrity test on differential signal structures with R&S®ZNB

Measurement of risetime, impedance, intra-pair skew, interpair-skew, etc. with the advanced time-domain option R&S®ZNB-K20.

Related products

Oscilloscopes

  • System level verification and debugging
  • Interface compliance testing
  • TDR / TDT testing

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Vector network analyzers

  • PCB and interconnect testing

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Signal & spectrum analyzers / Phase noise analyzers

  • Clock and PLL jitter measurements
  • Spurious measurements

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DC power supplies

  • Clean DC power for your digital design

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Related topics

High-speed digital interface testing

Test solutions for:

  • Design verification and debug test
  • Compliance test

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Power integrity testing

Test solutions for:

  • Power integrity test
  • Power delivery test

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Protocol-level debug testing

Test solutions for:

  • Trigger and decode of protocol patterns

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EMC testing

Test solutions for:

  • EMC compliance test
  • EMC pre-compliance test
  • EMC debugging test

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