Clock input monitoring, holdover and relocking with sampling clocks

10-Feb-2019

Clock and LO components in 5G base stations (part 3/3)

Clock input monitoring, holdover and relocking with sampling clocks

Monitoring and relocking clock inputs are critical for the performance and the timing of 5G base station transceivers. See how to measure the relocking period parameters of IDT’s RF sampling clock generator / jitter attenuator with vector signal generator R&S SMW200A incl. phase noise profile option and high-performance spectrum and phase noise analyzer R&S FSWP.

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