High-speed digital interface testing, PCIe testing

PCIe – peripheral component interconnect express

PCIe – Successfully verify and optimize your system design

Design verification and debugging - Compliance testing

The PCIe architecture is the core of most computer designs and connects the processor and memory subsystems to the endpoint devices via the root complex. The growing demand for speed is driving standardization efforts in PCI-SIG and their adoption in data centers, PCs and embedded applications. Working closely with PCI-SIG, Rohde & Schwarz provides a wide range of solutions for PCIe compliance testing.

In addition to compliance testing, Rohde and Schwarz PCIe test solutions help you efficiently verify and debug your design at the board and system level, including in the presence of other interfaces and wireless signals.

High-Speed-Digital webinars

PCIe 5.0 / 6.0 and IEEE802.3ck Cable Test – Signal Integrity, Performance Parameters, and Automation

This webinar is intended for engineers who work on high-speed digital design and test. Register now.

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PCI Express Gen 3 - compliance and debug testing

This webinar is intended for engineers who work on high-speed digital design and test. In particular, we will be focusing on PCIe Gen 3 interfaces. After an overview of PCIe technology, we will be discussing PCIe testing for compliance, protocol trigger and decode, and signal integrity debug purposes.

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Real-time deembedding with the R&S®RTP

Deembedding the test fixtures and cables is important for proper measurements in PCIe. With the option R&S®RTP-K122, the R&S®RTP offers real-time deembedding to measure and trigger on deembedded signals in real-time.

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Optimizing differential measurements on high-speed interfaces

The R&S®RT-ZM modular probe system offers measurements in differential mode and common mode as well as single-ended measurements. The ground connection prevents the circuit from floating and ensures stable and reproducible signals.

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Comparison of jitter measurements in time and frequency domain

Jitter can be measured in the time and frequency domains. While scope based TIE measurements allow measurement of all jitter types, phase noise analyzer based jitter measurements are restricted to clock signals – but offer unrivalled jitter sensitivity.

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Precise measurements on high-speed digital PCBs with the R&S®ZNB

With the R&S®ZNB-K20 extended time domain option, the R&S®ZNB provides accurate tests of eye diagram, rise time, skew, etc. on digital high-speed signal structures. Additional deembedding tools can be installed to remove the effects of lead-ins and lead-outs.

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Jitter Analysis with the R&S®RTO Oscilloscope

Jitter is a key concern in signal integrity analysis. With the R&S®RTP-K12 and R&S®RTO-K12 options, Rohde & Schwarz oscilloscopes can measure TIE jitter, period jitter, cycle-cycle jitter, etc. and offer result displays such as jitter track, histogram or spectrum.

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Verifying the true jitter performance of PCIe reference clocks (Refclk)

As data rates increase, the jitter limits for the PCIe Refclk are becoming tighter. Due to the superior jitter sensitivity of phase noise analyzers (PNA), the PCIe Gen5 specification has introduced PNA based testing to verify the true jitter performance of the Refclk.

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De-embedding and measuring a PCIe5 connector with R&S®VNA

By reference to settings and measurements with a vector network analyzer R&S®ZNA we are demonstrating the de-embedding process of a PCIe5 connector integrated in a test fixture.

Real-time deembedding with the R&S®RTP

Realtime deembedding of a signal path with the R&S®RTP-K122 option. The R&S®RTP not only acquires deembedded waveforms, it also allows triggering on this deembedded signal.

Signal integrity measurements with jitter analysis

Jitter analysis with the R&S®RTO

Measurement of TIE jitter with the R&S®RTO-K12 option. Analysis of TIE jitter of a clock signal in statistics, track, histogram and spectrum view to detect disturbances on the clock.

Signal integrity analysis on a USB-C cable with the R&S®ZNA

In combination with the time domain option R&S®ZNA-K2 and the extended time domain option R&S®ZNA-K20, the R&S®ZNA VNA offers a variety of signal integrity measurements. The device under test, a USB-C cable, is analyzed in frequency and time domain as well as in eye diagramm representation.

Eye diagram analysis with the R&S®ZNB: introduction

Eye diagram measurements and eye mask testing with the R&S®ZNB-K20 extended time domain option. This option can be used to analyze jitter and noise as well as to apply emphasis and equalization on the measured eye diagram.

Eye diagram analysis with the R&S®ZNB: how to set up the measurements

Signal integrity testing on differential signal structures with the R&S®ZNB

Measurement of rise time, impedance, intra-pair skew, inter-pair skew, etc. with the R&S®ZNB-K20 extended time domain option.

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PCIe – peripheral component interconnect express

PCIe – Successfully verify and optimize your system design

Design verification and debugging - Compliance testing

High-Speed-Digital webinars

PCIe 5.0 / 6.0 and IEEE802.3ck Cable Test – Signal Integrity, Performance Parameters, and Automation

PCI Express Gen 3 - compliance and debug testing

Real-time deembedding with the R&S®RTP

Optimizing differential measurements on high-speed interfaces

Comparison of jitter measurements in time and frequency domain

Precise measurements on high-speed digital PCBs with the R&S®ZNB

Jitter Analysis with the R&S®RTO Oscilloscope

Verifying the true jitter performance of PCIe reference clocks (Refclk)

De-embedding and measuring a PCIe5 connector with R&S®VNA

Real-time deembedding with the R&S®RTP

Jitter analysis with the R&S®RTO

Signal integrity analysis on a USB-C cable with the R&S®ZNA

Eye diagram analysis with the R&S®ZNB: introduction

Eye diagram analysis with the R&S®ZNB: how to set up the measurements

Signal integrity testing on differential signal structures with the R&S®ZNB

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