Verifying power sequencing for FPGAs, CPUs and DSPs

Your task

When powering up complex electronic components like FPGAs or CPUs, several supply voltages need to be applied in a specific order and with certain delay or ramp-up times. It is necessary to minimize current draw and ensure that the I/Os are in a high-impedance state at power-up.

The recommended power-down sequence is usually the reverse of the power-up sequence. If these sequences are not followed, the current can exceed the specified limits which may lead to the component malfunctioning or being damaged. During circuit design, it is important to capture and analyze the characteristics of several voltages during startup and shutdown, as well as power breakdown.

Example power-up sequence of various supply voltages (indicated on the left) of a DSP of type TMS320C6652/4 from Texas Instruments Incorporated.

Rohde & Schwarz solution

The R&S®RT-ZVC is a multi-channel oscilloscope probe that provides up to four voltage and four current channels with a very high dynamic measurement range. Each channel has an ADC with 18-bit resolution at 5 Msample/s and 1 MHz bandwidth. With up to two R&S®RT-ZVC probes supported on a four-channel R&S®RTE1000 or R&S®RTO2000 oscilloscope, up to 20 voltages can be analyzed in parallel. For this configuration, the current channels have to be operated as a high-sensitivity voltmeter in external shunt mode.

Advanced analysis functions

To verify power-up and power-down sequences of FPGAs and CPUs, the startup and shutdown behavior of their supply voltages has to be characterized. In particular, there are several voltage properties that need to fulfill certain requirements:

• Power-on/power-down delay: The different supply voltages need to be applied with specific time delays that can range from a few nanoseconds to several milliseconds depending on the specific device
• Certain voltage ramp-up times: The levels of the different supply voltages of FPGAs, CPU and DSPs are usually between 1 V and 5 V. In addition, each voltage has recommended minimum and maximum ramp-up times that range from a few microseconds to several milliseconds. Therefore, the recommended slew rates range from a few V/μs to several V/ms
• Difference between supply voltages: During ramp-up (see above), the difference between particular voltages should not exceed defined values

The R&S®RTE1000 and R&S®RTO2000 oscilloscopes are powerful tools for verifying the required power sequencing parameters. The specific voltage characteristics can be analyzed using the oscilloscopes’ integrated measurement and math functions:

• Cursors allow manual analysis of multiple parameters, such as the delay between different channels
• Automated measurement functions allow straightforward determination of properties such as delay between channels or rise time of individual voltages. In addition, the sampling rate of 5 Msample/s of the R&S®RT-ZVC is sufficient to measure typical slew rates of several volts per millisecond
• Math functions between individual oscilloscope channels can verify the required voltage difference

Excellent accuracy for tight supply voltage tolerances

In addition to power sequencing, stable and clean power rail voltages are the basis for decent performance of almost any electronic design. In general, power rail voltages and their tolerance windows are decreasing to minimize power consumption and improve battery lifetime.

To analyze the small supply voltages and the tight tolerance windows of FPGAs or CPUs, the measurement device needs a certain sensitivity and accuracy. The R&S®RT-ZVC has an excellent accuracy of 0.1 % for voltage measurements and 0.2 % for current measurements, which is more than 10 times higher than standard oscilloscope channels.

Summary

The R&S®RT-ZVC is an ideal multi-channel power probe for straightforward visualization of startup and shutdown sequences of FPGA and CPU supply voltages. It supports simple measurement of delay, ripple noise and ramp-up time on individual channels to verify the accuracy and correctness of the power sequencing process.