High-speed digital interface testing, DDR testing

DDR – double data rate memory

Efficiently verify and debug your DDR design

Design verification and debugging - Compliance testing

The need for increasing speed, higher memory size and power efficiency is driving the evolution in DDR and LPDDR interface technology as defined by JEDEC. Working closely with JEDEC, Rohde & Schwarz provides powerful solutions for DDR compliance testing.

As part of the overall design, DDR memory controller and memory devices also need to properly work in the presence of other high-speed interfaces or even wireless signals. In addition to compliance testing, Rohde and Schwarz DDR test solutions help you efficiently verify and debug your design at the board and system level.

  • Oscilloscopes for interface verification, debug, comliance test and TDR analysis
  • Network analyzers for PCB and interconnect analysis
Step-by-step guide: Advanced probing in DDR3/DDR4 memory design

Step-by-step guide

Advanced probing in DDR3/DDR4 memory design

When testing designs with DDR memories, it is equally important to look into the measurement techniques as well as the probing solutions. Selecting the right probe, probing at the right place, modifying probe tip impedance to compensate interposer resistors and improving the measurement accuracy through deembedding are important to achieve repeatable and accurate test results.

Application Guide: System Verification and Debug of DDR3/4 Memory Designs

Application guide

System verification and debug of DDR3/4 memory designs

  • DDR memory technology
  • common design challenges
  • verification and debug strategies
  • typical measurements
DDR memory system design verification and debug webinar

Webinar

DDR memory system design verification and debug

Get best practices of doing the DDR memory system design verification and debugging with an oscilloscope. Design and verification engineers will be learning the importance of ensuring a stable operation and of reducing the risk of failure after any change over the product’s lifetime.

Related documents

Efficient eye diagram testing in DDR3/DDR4 system designs

When debugging DDR SI issues, tools like mask test, eye diagram and read/write separation are needed to facilitate the analysis effort. The R&S®RTx-K91 (DDR3/DDR3L/LPDDR3) and R&S®RTx-K93 (DDR4/ LPDDR4) options offer the full tool chain, from DDR system validation and debug to compliance test.

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Triggering read and write cycles of DDR3 memories

Reliably separating read/write cycles is crucial for analyzing the signal integrity of DDR memory interfaces. The R&S®RTP oscilloscope's digital trigger and zone trigger provide versatile and flexible triggering capabilities for tests on DDR memory interfaces.

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Real-time deembedding with the R&S®RTP

It is necessary to deembed the interposer characteristics to get measurement results at the BGA interface of the DDR memory device. With the R&S®RTP-K122 option, the R&S®RTP offers real-time deembedding to measure and trigger on deembedded signals in real time.

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Optimizing differential measurements on high-speed interfaces

The R&S®RT-ZM modular probe system offers measurements in differential mode and common mode as well as single-ended measurements. The ground connection prevents the circuit from floating and ensures stable and reproducible signals.

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Enhancing channel-to-channel alignment for accurate multichannel acquisition

Measurement and alignment of channel-to-channel skew is an important prerequisite, when doing accurate multichannel measurements. R&S®RTO and R&S®RTP oscilloscopes provide an optional high-speed differential pulse source (R&S®RTO-B7 and R&S®RTP-B7) to facilitate this alignment.

More information

Related videos

DDR3 signal integrity debugging

DDR3 signal integrity debugging with the R&S®RTP

Signal integrity debugging on a DDR3 device using the R&S®RTP-K91 DDR3/LPDDR3 signal integrity debug and compliance test software.

Realtime deembedding

Real-time deembedding with the R&S®RTP

Realtime deembedding of a signal path with the R&S®RTP-K122 option. The R&S®RTP not only acquires deembedded waveforms, it also allows triggering on this deembedded signal.

Signal integrity testing on differential signal structures with the R&S®ZNB

Signal integrity testing on differential signal structures with the R&S®ZNB

Measurement of rise time, impedance, intra-pair skew, inter-pair skew, etc. with the R&S®ZNB-K20 extended time domain option.

Signal integrity measurements with jitter analysis

Jitter analysis with the R&S®RTO

Measurement of TIE jitter with the R&S®RTO-K12 option. Analysis of TIE jitter of a clock signal in statistics, track, histogram and spectrum view to detect disturbances on the clock.

Eye diagram analysis with the R&S®ZNB: introduction

Eye diagram analysis with the R&S®ZNB: introduction

Eye diagram measurements and eye mask testing with the R&S®ZNB-K20 extended time domain option. This option can be used to analyze jitter and noise as well as to apply emphasis and equalization on the measured eye diagram.

Eye diagram analysis with the R&S®ZNB: how to set up the measurements

Eye diagram analysis with the R&S®ZNB: how to set up the measurements

Eye diagram measurements and eye mask testing with the R&S®ZNB-K20 extended time domain option. This option can be used to analyze jitter and noise as well as to apply emphasis and equalization on the measured eye diagram.

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