DDR memory system design verification and debug

Presented by Johannes Ganzert and Hermann Ruckerbauer

DDR memory system design verification and debugs

Design and verification engineers will be learning the importance of ensuring a stable operation and of reducing the risk of failure after any change over the product’s lifetime. Both require a solid characterization of the memory interface.

We will be discussing test and tool requirements such as bandwidth, trigger and probing, which help with identifying jitter, timing and noise issues. With the help of the R&S®RTP high-performance oscilloscope, we will showcase practical measurement examples.