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Top content about Clock & Timing

Phase noise Jitter Development

Verifying additive phase noise and jitter attenuation of PLLs in high-speed digital designs

Increasing data rates in digital designs and wireless communications require SerDes PLLs and clock synthesizers with low additive phase noise and high jitter ...

Data converter design 5G Signal generators

Demystifying 5G – RF sampling ADCs: how to verify modulation performance?

Explore how to verify the modulation performance of a high speed ADC on the digital side using direct synthesis and direct sampling at RF frequencies.

Clock & Timing Videos

Data converter design 5G Signal generators

Demystifying 5G – RF sampling ADCs: how to verify modulation performance?

Explore how to verify the modulation performance of a high speed ADC on the digital side using direct synthesis and direct sampling at RF frequencies.

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Clock & Timing Data converter design Signal generators

First class ADCs thanks to first class signals

This video presents how the R&S®SMA100B supports you in measuring the true performance of ADCs and provides you with the purest signals. Watch to learn more.

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Clock & Timing Phase noise 5G

Clock and LO components in 5G base stations (part 3/3)

See how to measure the relocking period parameters of RF sampling clock generator / jitter attenuator with vector signal generator R&S®SMW200A incl. phase ...

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Clock & Timing Jitter Oscillators PLLs

Clock and LO components in 5G base stations (part 2/3)

Learn how to verify the performance of RF sampling clock generator / jitter attenuator with low noise signal generator R&S®SMA100B and high-performance ...

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Clock & Timing Oscillators PLLs Signal generators

Clock and LO components in 5G base stations (part 1/3)

See how to achieve excellent phase noise measurement results with low noise signal generator R&S®SMA100B and phase noise analyzer R&S®FSWP

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Clock & Timing Phase noise Data converter design

Demystifying 5G – Phase noise of clock and LO components in 5G base stations

The video demonstrates a clock generator and an RF synthesizer from IDT and shows the measurement of the phase noise, contributed by these components.

Clock & Timing Application Cards & Notes

Phase noise Jitter Development

Verifying additive phase noise and jitter attenuation of PLLs in high-speed digital designs

Increasing data rates in digital designs and wireless communications require SerDes PLLs and clock synthesizers with low additive phase noise and high jitter ...

Clock & Timing Data converter design Signal generators

When you need an ideal clock source

You need a flexible clock source that can provide the signals needed for today’s and tomorrow’s designs with minimal jitter and noise as well as best spectral ...

Jitter Phase noise Development

Verifying the clock source

The R&S FSWP phase noise analyzer is the perfect tool for verifying clock sources to ensure accuracy of design requirements and proper operation.

Data converter design Signal generators Clock & Timing

Testing True Performance of ADCs using R&S®SMA100B Signal Generator

The R&S®SMA100B offers outputs for the analog input signal of the ADC as well as the clock input signal in one single instrument - both with outstanding ...