Signal integrity test

Signal Intergrity: Clock tree, PLL and ADC/DAC test

Newest high-speed technologies require both, ultra-low jitter reference clocks as well as ultra-low jitter transmitter and receiver designs in the SoCs (System on Chip). New test methodologies are required, overcoming the limitations in jitter measurement floor of existing methods and measuring the true jitter performance of a reference clock or SerDes PLL. This jitter performance also needs to be achieved in a real-life Power Integrity environment of a system design, with its power rail disturbances inducing jitter to the clock or SerDes PLL. This is typically characterized by the power supply noise rejection ratio PSNR. With the increasing complexity in high-speed technologies like 112Gbps Ethernet, ADC/DAC based equalization are being used and the corresponding analog-to-digital and digital-to-analog data converters need to be designed and characterized.

With expertise in both the time and frequency domain and by working closely with the corresponding standardization bodies, Rohde & Schwarz provides powerful solutions to meet the new challenges in clock tree, SerDes PLL and ADC/DAC Test.

Documents for Clock tree, PLL and ADC/DAC test

Verifying additive phase noise and jitter attenuation of PLLs in high-speed digital designs

SerDes PLLs in high-speed digital SoCs need to be designed for ultra-low jitter. Due to its high phase noise sensitivity, the R&S®FSWP phase noise analyzer is the instrument of choice for these tests.

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Verifying the true jitter performance of clocks in high-speed digital designs

With growing data rates, the jitter limits for PCIe Refclks are getting tighter. Due to their superior jitter sensitivity, the PCIe Gen5 specification has introduced Phase Noise Analyzer based testing to verify the true jitter performance of a Refclk.

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Measuring power supply induced jitter and PSNR in low jitter oscillators and clocks

Low jitter oscillators and clocks deliver best performance with clean power rails. As part of an overall system design, they also have to perform in a non-ideal power integrity environment and properly suppress power supply induced phase noise and jitter.

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Verifying the clock source

The signal purity of clock sources has a direct impact on the overall system performance. To ensure proper operation, it is necessary to verify that the purity meets the design requirements.

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Comparison of jitter measurements in the time and frequency domain

Jitter can be measured in both time and frequency domain. While scope-based TIE measurements include all jitter types, phase noise analyzer based jitter measurements are restricted to clock signals; with an unrivalled jitter sensitivity.

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A 1 MHz to 50 GHz Direct Down-Conversion Phase Noise Analyzer with Cross-Correlation

The R&S®FSWP offers a frequency range from 1 MHz to 50 GHz with direct down-conversion, analog I/Q mixers and baseband signal sampling. The traditional PLL concept is replaced by a digital FM/AM demodulator for concurrent measurement of phase and amplitude noise.

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Measurement Setup for Phase Noise Test at Frequencies above 50 GHz

With external mixers, the R&S®FSWP offers phase noise measurements beyond 50GHz. Cross-correlation can be used to further reduce the internal phase noise contribution of the test setup.

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Videos for Clock tree, PLL and ADC/DAC test

Signal integrity measurements with jitter analysis

Jitter analysis with R&S®RTO

Measurement of TIE jitter with R&S®RTO oscilloscope option K12. Analysis of TIE jitter of a clock signal in statistics, track, histogram and spectrum view to detect disturbances on the clock.

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