Hardware Development : Sr Layout Engineer

Your tasks

• Perform layout of transistor-level circuits, perform integration of circuit blocks, and manage layout integration to final tape-out
• Use Virtuoso GXL, chip assembly router, bus router and constraint editor to manage and maintain layouts of complex nature
• Complete foundry signoffs for LVS/DRC and other physical verification checks
• Ensure parasitic minimization on critical nets, ensure proper matching, LVS/DRC compliance
• Assist the project lead with aggressive but realistic layout related tape out schedule planning
• Contribute to full-chip physical design methodologies and floor planning

Your qualifications

• Ten (10+) years of RFIC layout experience
• Successfully tape out a minimum of 5 dies on at least two different processes.
• Proficient in the Cadence Virtuoso GXL/XL layout suite.
• Experience with floor-planning, flat as well as hierarchical, top-down flows
• Experience in IO ring creation, package planning, checks
• Expertise in high frequency/high performance layout techniques
• High frequency differential signal routing
• Transmission line routing
• Expertise in power mesh and clock routing
• Experience in creating tape out ready database;
• Solid understanding of EM/IR analysis, latch-up, signal integrity and ESD
• Understand tradeoffs between power density and signal integrity
• Highly motivated to meet deadlines during chip tape-out.
• Ability to travel occasionally to European and U.S. locations.
• Ability to speak fluently and read/write clearly in English. Desirable qualifications. The more of these that you have, the better fit within our team.
• BS or higher in electrical engineering
• Experience with skill scripting in constraint editor
• Ability to assist the P&R team on DRC/LVS closure.
• Layout experience using BiCMOS processes

Interested?