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This application note provides an introduction to the DDR memory technology and explains common challenges, related to the specific nature of DDR data, command ...
Verification and debugging of the interface is a difficult task. We look at the main design and debugging challenges and discuss best practices.
Get best practices of doing the DDR memory system design verification and debugging with an oscilloscope in our On-demand webinar.
DDR3 signal integrity debugging
This option supports Signal Integrity debugging and automated compliance testing of DDR3, DDR3L and LPDDR3 memory interfaces
For system verification and debugging, eye diagram measurements are the most important tools for efficiently analyzing the signal integrity in any digital design
The digital trigger of the R&S®RTP combined with the zone trigger offers versatile and flexible triggering capabilities for DDR memory interface measurements.
Verifying power integrity for DDR memories - The R&S ® RT-ZPR20 power rail probe is a specialized oscilloscope probe for very low-noise measurements on power.