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Generating models with a VNA and using these on an oscilloscope via the deembedding
Get best practices of doing the DDR memory system design verification and debugging with an oscilloscope in our On-demand webinar.
Register for this webinar that is intended for engineers who work on high-speed digital design and test.
In this webinar your will learn more about efficiently triggering and decoding low-speed serial buses with solutions from Rohde & Schwarz.
Register for this webinar and learn more about USB 3.2 compliance testing with oscilloscopes from Rohde & Schwarz.
This webinar is intended for engineers who work on the design and testing of high-speed interfaces. We will start with typical design challenges and methods in ...
This option supports Signal Integrity debugging and automated compliance testing of DDR3, DDR3L and LPDDR3 memory interfaces
This application note provides an introduction to the DDR memory technology and explains common challenges, related to the specific nature of DDR data, command ...
This application note proposes a digital level shifter for connecting the I2S interfaces R&S®UPP-B2 and R&S®UPV-B41 to devices under test with a logic ...
Due to their high phase noise sensitivity, phase noise analyzers are the instruments of choice for these tests.
The ground connection on the R&S®RT‑ZMxx modular multimode probes can be used to improve measurements on high-speed differential interfaces.