Signal Intergrity: Clock tree, PLL and ADC/DAC test
Newest high-speed technologies require both, ultra-low jitter reference clocks as well as ultra-low jitter transmitter and receiver designs in the SoCs (System on Chip). New test methodologies are required, overcoming the limitations in jitter measurement floor of existing methods and measuring the true jitter performance of a reference clock or SerDes PLL. This jitter performance also needs to be achieved in a real-life Power Integrity environment of a system design, with its power rail disturbances inducing jitter to the clock or SerDes PLL. This is typically characterized by the power supply noise rejection ratio PSNR. With the increasing complexity in high-speed technologies like 112Gbps Ethernet, ADC/DAC based equalization are being used and the corresponding analog-to-digital and digital-to-analog data converters need to be designed and characterized.
With expertise in both the time and frequency domain and by working closely with the corresponding standardization bodies, Rohde & Schwarz provides powerful solutions to meet the new challenges in clock tree, SerDes PLL and ADC/DAC Test.
