R&S®SMW-K551 Slow I/Q

The design flow of a digital chipset or module can be subdivided into several steps. Signal generators are typically used at two stages:

  • Signal generation for stimulating hardware simulators that emulate a chip or module design
  • Verification and test of early hardware prototypes (chipset, SoC, digital module)

Stimulus generation for HW emulators

During the design process of chipsets or modules, FPGA-based hardware emulators are utilized to perform early tests with real test and measurement instruments. At this stage the chip/module design only exists as SW model. The generic HW emulator runs this SW model and allows stimulation with real physical signals. Via the R&S®EX-IQ-Box the digital IQ signal from the R&S®SMW200A is physically converted to the needed digital IQ signal of the HW emulator. The R&S®SMW-K551 Slow IQ option is used to slow down the stimulus generation to meet the clock rate requirements of the hardware emulator.

Stimulus generation for HW prototypes

For design verification of digital hardware prototypes, the R&S®SMW200A is used to supply the needed digital IQ stimulus signals. The DUT can be any device with a digital IQ interface such as an FPGA based test board, an adapter board with the chipset/SoC to test or a completely integrated digital signal processing module. Typically, the whole test bed is controlled via chipset/DUT specific debug tools. The R&S®SMW-K551 Slow IQ option is used to adapt the signal generation speed to the processing speed of the HW prototype. The R&S®EX-IQ-Box “translates” the digital IQ signal from the R&S®SMW200A to the data format needed by the DUT. All in all, this allows general functionality and algorithm tests with realistic signals for early design prototypes that are not capable to run at full speed.

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