High-speed digital interface testing, PCIe testing

PCIe test solutions

Testing PCIe (peripheral component interconnect express)

Practically all requirements for testing PCIe data transmissions and signal properties are met by oscilloscopes, both during development and for PCIe compliance test. On the physical layer, network analyzers can provide the highest possible precision for signal integrity test. With an automated network analyzer test setup only available from Rohde & Schwarz,dramatically reduce times for testing signal integrity parameters and increase test reliability for PCIe cables and connectors with four or more lanes, using the 5.0 or 6.0 specification.

PCIe is the de-facto standard for a server or PC mainboard interconnect, between the main processor and both integrated-peripherals (surface mounted chips) and plug-in peripherals (expansion cards) such as graphic cards or memory cards, or add-in boards. For PC manufacturers and chip and plug-in board suppliers throughout the industry, verifying PCIe interfaces during development, and subsequently for function verification and production quality control is an essential task.

First introduced in 2003 as PCIe 1.0 with a bandwidth of 8 GB/s running at a frequency of 2.5 GHz supporting 2.5 Giga transfers per second (GT/s), a new upgraded version has been released by the PCI-SIG (Special Interest Group) every couple of years, each time doubling the performance. The latest version released in 2022 is PCIe 6.0 with a bandwidth of 256 GB/s running at a frequency of 32 GHz supporting 64 GT/s. Data rates are shown as transfers per second, not the bit rate. This is due to the transmission coding converting data bits to a larger number of transmission characters in order to reduce transmission errors at the cost of an increased amount of information to transmit. For PCI 1.0 and 2.0 8b/10b coding is used, for 3.0 the transmission overhead is greatly reduced with 128b/130b coding. Transmission errors are reduced by achieving DC balance and bounded disparity (long term, 50% “1” and 50% “0” are transmitted).

While 128/130b reduces the protocol overhead from 25% to 1.5%, the protocol-based transmission error correction is also reduced. PCIe 3.0 added receiver equalization to compensate for in-channel frequency response at higher frequencies. Sophisticated algorithms aim to create digital filters matching the channel loss at the receiver.

PCIe connects by 1 or more lanes in a slot. A lane contains a transmit and receive pair of differential lines, so each lane is a full-duplex stream, transporting data packets. PCIe slots may contain from one to thirty-two lanes, in powers of two. Lane counts are written with an x prefix (e.g., x16 represents a sixteen-lane card or slot), with x16 being the largest size in common use. An x1 slot transmits data at 1 bit per cycle, an x16 slot at 16 bits per cycle. Both in terms of slots and versions PCIe is fully backwards compatible, with the data rate determined by the smaller slot size, and the lower version.

The commercial implementation of PCIe lags several versions behind the latest standard. There are still more 3.0 PC motherboards available than 4.0, which in turn outnumbers the 5.0 mother boards; the number of applications requiring data rates of more than 16 GT/s are strictly limited. For simpler processors running many industrial and commercial devices, PCIe 1.0 provides more than enough performance.

Your PCIe test challenge

  • For PCIe cables and connectors with four or more lanes using the 5.0 or 6.0 specification, how to test signal integrity requiring hundreds of measurements, reliably and in an acceptable time scale and with suitable test procedures? Considering that you need to match the varying requirements measurements during development, compliance test, and production.
  • How to read the content of PCIe messages? A consequence of the transmission coding converting data bits to a larger number of transmission characters is that reading data directly from the data stream is not possible. Receiver equalization algorithms add an additional complication to decoding message content.
  • How to evaluate the quality and signal integrity of data transmissions, and check compliance to jitter tolerances.
  • Compliance testing consists of a series of procedures that must be strictly adhered to, if the results are to be valid; you need to be sure you are conducting compliance tests correctly. An additional complication in the PCIe test procedures is the need to select the correct test signal from one of several for each test.

Our PCIe test solutions

For PCIe cables and connectors meeting 5.0 or 6.0 specification, you can measure all required signal integrity parameters with an automated test setup including an R&S®ZNB43 network analyzer for measurements, the R&S®OSP320 open switch and control platform for multiport switching, and the R&S®ZNrun-K440 option to automate the test procedures.

Both R&S®RTO64 and R&S®RTP oscilloscopes provide the required performance for investigating PCIe 1.0 and PCIe 2.0. signals. The R&S®RTP can also investigate PCIe 3.0 signals. Dedicated PCIe options for both oscilloscopes provide both trigger on and decode for PCIe signals to debug and verify the performance:

  • PCIe 1.0 with an R&S®RTO64 or R&S®RTP (bandwidths 6-16 GHz). Run all PCIe 1.0 compliance tests on for all slot sizes (x1/4/8/16) and the maximum data rate 2.5 GT/s), with option K81. Trigger on, decode, and search the protocol detail with option K72.
  • PCIe 2.0 on an R&S®RTO64 or R&S®RTP (bandwidths 6-16 GHz). Run all PCIe 1.0 compliance tests on PCIe 2.0 for all slot sizes (x1/4/8/16) to a maximum data rate of 2.5 GT/s with an R&S®RTO64. or the maximum data rate (5.0 GT/s) with R&S®RTP, and option K81. Trigger on, decode, and search the protocol detail with option K72.
  • PCIe 3.0 on an R&S®RTP (bandwidths 13-16 GHz). Run all PCIe 3.0 compliance tests for all slot sizes (x1/4/8/16) and the maximum data rate (8 GT/s), with option K83. Trigger on, decode, and search the protocol detail with option K73. Trigger on decoded data with option K140/K141.

The bandwidth of the oscilloscope is the most significant factor for determining which signals can be acquired, and for which test purpose. For debug the bandwidth should cover the 3rd harmonic of the fundamental frequency of the required signal, for compliance test the 5th harmonic.

To simplify and automate compliance test procedures with oscilloscopes, the R&S®ScopeSuite provides:

  • A comprehensive Graphical Wizard to guide through the compliance procedures from beginning to end.
  • Automated control of all necessary oscilloscope settings and compliance test sequences.
  • Configurable test reports to document the test results.

Rohde & Schwarz also supplies all the necessary accessories such as highspeed probes for PCIe debug, signal integrity test, validation and compliance test.

For PCIe interface testing, Rohde & Schwarz network analyzers (R&S®ZNA, R&S®ZNB) provide signal integrity measurements with a dynamic range and maximum bandwidth that comfortably exceeds all PCIe requirements. For both analyzer families, option K2 plus K20 provides time domain analysis including eye diagrams and simultaneous frequency domain analysis.

Benefits of our PCIe test solutions

At all stages of interconnect and cable development from R&D to production, an automated network analyzer setup handles all the complexities of the test procedure with complete reliability, and reduces test durations by a factor of 10 or more.

Be confident that the results of your compliance tests are valid. All Rohde & Schwarz compliance test options fully implement the PCI Special Interest Group (PCI-SIG) official compliance test software for signal quality and reference clock tests and data eye verification.

Compliance test requires several test signal patterns. With the arbitrary waveform generator (option B6) installed, Rohde & Schwarz oscilloscopes switch automatically between the test signals as required, both saving test time and ensuring that the correct waveform is always selected.

Compensate for skew between oscilloscope channels at higher PCIe frequencies with option B7 as pulse source for channel de-skew.

The R&S®RTP features the most comprehensive set of debug and analysis tools for PCIe available:

  • Trigger and search on protocol detail such as Transaction Layer Packets, Data Layer
  • Packets, Ordered Sets and Errors. Selectable decoding level from bits to final protocol content, to meet your needs.
  • A consequence of the transmission coding is that reading data directly from the data stream is not possible. R&S®RTP- K140/141 include Clock Data Recovery which extracts the embedded clock from the signal, so that decoded data can be triggered on; a very powerful tool for debugging.
  • Receiver equalization compensation for signal integrity loss at the receiver, providing accurate bit recovery and low bit error rates for PCIe 3.0. The two most common receiver equalization algorithms are included in the trigger and decode functions; continuous-time linear equalization (CTLE), and decision feedback (DFE), including non-linear filtering.
  • Eye diagrams provide a simple graphic tool for evaluating the quality and integrity of data signals. Based on the unique Rohde & Schwarz oscilloscope digital trigger hardware, R&S®RTP- K136/K137 provide eye analysis in close to real time for high speed digital interfaces, such as PCIe.
  • Conforming to Jitter tolerances (signal timing disturbances) is a PCIe requirement. Analyze jitter with R&S®RTP- K133.

Signal loss is inevitable between the point where a signal is acquired and it reaching the measuring instrument input, caused by the probes, adapters and cables in the setup. The higher the frequency, the greater the signal loss. Option R&S®RTP K122 includes a simple to use setup for specifying components to de-embed, so correcting for the transmission losses using computations based on S-parameters.

Do you have further questions about our PCIe compliance testing solutions?
Then feel free to contact us.

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